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MC68HC901
Multi-Function Peripheral User's Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) 1995 Motorola, Inc. All Rights Reserved.
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Applications and Technical Information
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PREFACE
The complete documentation package for the MC68HC901 consists of the MC68HC901UM/ AD and the M68000 Family Programmer's Reference Manual, which contains the complete instruction set for the M68000 Family. The MC68HC901 Multi-Function Peripheral User's Manual describes the programming, capabilities, registers, and operation of the MC68HC901. This device is the HCMOS version of the older MC68901 device and provides enhanced performance in several areas. The MC68HC901 provides a full-function single-channel USART, an eight-source interrupt controller, four 8-bit timers, and eight parallel I/O lines. The organization of this manual is as follows: Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Section 8 Section 9 Introduction Signal Description Bus Operation Interrupt Structure General Purpose Input/Output Port Timers Universal Synchronous/Asynchronous Receiver-Transmitter Electrical Characteristics Mechanical Data and Ordering Information
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TABLE OF CONTENTS
Paragraph Number Title Section 1 Introduction Page Number
2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.8 2.9 2.9.1 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3 2.10.4 2.11 2.11.1 2.11.2 2.12
Power Supply (VCC and GND) .................................................................. Clock (CLK) .............................................................................................. Data Bus (D7-D0) .................................................................................... Asynchronous Bus Control ....................................................................... Chip Select (CS) .................................................................................. Data Strobe (DS) ................................................................................. Read/Write (R/W) ................................................................................ Data Transfer Acknowledge (DTACK) ................................................. Register Select Bus (RS1-RS5) ............................................................... Reset (RESET) ......................................................................................... Interrupt Control ........................................................................................ Interrupt Request (IRQ) ....................................................................... Interrupt Acknowledge (IACK) ............................................................. Interrupt Enable In (IEI) ....................................................................... Interrupt Enable Out (IEO) ................................................................... General Purpose I/O Interrupt Lines (I7-I0) ............................................. Timer Control ............................................................................................ Timer Inputs (TAI and TBI) .................................................................. Timer Outputs (TAO, TBO, TCO, and TDO) ....................................... Timer Clock (XTAL1 and XTAL2) ........................................................ Serial I/O Control ...................................................................................... Serial Input (SI) .................................................................................... Serial Output (SO) ............................................................................... Receiver Clock (RC) ............................................................................ Transmitter Clock (TC) ........................................................................ Direct Memory Access Control ................................................................. Receiver Ready (RR) .......................................................................... Transmitter Ready (TR) ....................................................................... Signal Summary .......................................................................................
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1.1 1.2
Key Features .............................................................................................1-2 Register Programming ...............................................................................1-2
2-1 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-3 2-3 2-3 2-4 2-4 2-4 2-4 2-4 2-4 2-5 2-5 2-5 2-5 2-5 2-5 2-5
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TABLE OF CONTENTS (Continued)
Paragraph Number Title Section 3 Bus Operation 3.1 3.1.1 3.1.2 3.2 3.3 Data Transfer Operations ......................................................................... Read Cycle .......................................................................................... Write Cycle .......................................................................................... Interrupt Acknowledge Operation ............................................................. Reset Operation ....................................................................................... Section 4 Interrupt Structure 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.4.1 4.4.2 4.4.3 Interrupt Processing ................................................................................. 4-1 Interrupt Channel Prioritization ............................................................ 4-1 Interrupt Vector Number ...................................................................... 4-1 Vector Register (VR) ........................................................................... 4-2 Daisy-Chaining MFPs ............................................................................... 4-3 Interrupt Control Registers ....................................................................... 4-4 Interrupt Enable Registers (IERA, IERB) ............................................ 4-4 Interrupt Pending Registers (IPRA, IPRB) .......................................... 4-6 Interrupt Mask Registers (IMRA, IMRB) .............................................. 4-8 Interrupt In-Service Registers (ISRA, ISRB) ..................................... 4-10 Nesting MFP Interrupts ........................................................................... 4-11 Selecting the End-Of-Interrupt Mode ................................................. 4-11 Automatic End-Of-Interrupt Mode ..................................................... 4-12 Software End-Of-Interrupt Mode ....................................................... 4-12 Section 5 General Purpose Input/Output Port 5.1 5.1.1 5.1.2 5.1.3 GPIP Control Registers ............................................................................ General Purpose I/O Data Register (GPDR) ....................................... Active Edge Register (AER) ................................................................ Data Direction Register (DDR) ............................................................ Section 6 Timers 6.1 6.1.1 6.1.2 6.1.3 6.2 Operation Modes ...................................................................................... Delay Mode Operation ........................................................................ Pulse Width Measurement Operation ................................................. Event Count Mode Operation .............................................................. Timer Registers ........................................................................................ 6-1 6-1 6-2 6-3 6-4 5-1 5-1 5-1 5-2 3-1 3-1 3-2 3-2 3-3 Page Number
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TABLE OF CONTENTS (Continued)
Paragraph Number 6.2.1 6.2.2 Title Page Number
Timer Data Registers (TxDR) .............................................................. 6-4 Timer Control Registers (TxCR) .......................................................... 6-4 Section 7 Universal Synchronous/Asynchronous Receiver-Transmitter
7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.2.1 7.2.2 7.2.3 7.3 7.3.1 7.3.2 7.4
Character Protocols .................................................................................. Asynchronous Format ......................................................................... Synchronous Format ........................................................................... USART Control Register (UCR) .......................................................... USART Data Register (UDR) .............................................................. Receiver .................................................................................................... Receiver Interrupt Channels ................................................................ Receiver Status Register (RSR) .......................................................... Special Receive Conditions ................................................................. Transmitter ................................................................................................ Transmitter Interrupt Channels ............................................................ Transmitter Status Register (TSR) ...................................................... DMA Operation ......................................................................................... Section 8 Electrical Characteristics
7-1 7-2 7-2 7-3 7-4 7-4 7-5 7-5 7-7 7-7 7-8 7-8 7-9
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8
Maximum Ratings ..................................................................................... Thermal Characteristics ............................................................................ Power Considerations ............................................................................... DC Electrical Characteristics .................................................................... Capacitance .............................................................................................. Clock Timing ............................................................................................. AC Electrical Characteristics .................................................................... Timer AC Characteristics .......................................................................... Section 9 Mechanical Data and Ordering Information
8-1 8-1 8-2 8-3 8-3 8-4 8-5 8-7
9.1 9.2 9.3
Pin Assignments ....................................................................................... 9-1 Package Dimensions ................................................................................ 9-2 Ordering Information ................................................................................. 9-4
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LIST OF ILLUSTRATIONS
Figure Number 1-1. 2-1. 3-1. 3-2. 3-3. 4-1. 4-2. 6-1. 8-1. 8-2. 8-3. 8-4. 8-5. 8-6. 8-7. 8-8. 8-9. 8-10. 8-11. 8-12. 9-1. 9-2. 9-3. 9-4. Title Page Number
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MFP Block Diagram ........................................................................................ 1-1 Input and Output Signals ................................................................................ 2-1 Read Cycle Timing Diagram ........................................................................... 3-2 Write Cycle Timing Diagram ........................................................................... 3-2 IACK Cycle Timing Diagram ........................................................................... 3-3 Daisy-Chained Interrupt Structure ................................................................... 4-3 Conceptual Circuits of an Interrupt Channel ................................................... 4-9 Conceptual Circuit of Interrupt Source Selection ............................................ 6-2 Clock Input Timing Diagram ............................................................................ 8-4 MFP External Oscillator Components ............................................................. 8-4 Read Cycle Timing .......................................................................................... 8-8 Write Cycle Timing .......................................................................................... 8-8 Interrupt Acknowledge Cycle (IEI Low) ........................................................... 8-9 Interrupt Acknowledge Cycle (IEI High) ........................................................ 8-10 Interrupt Timing ............................................................................................. 8-10 Port Timing .................................................................................................... 8-10 Reset Timing ................................................................................................. 8-11 Receiver Timing ............................................................................................ 8-11 Transmitter Timing ........................................................................................ 8-11 Timer Timing ................................................................................................. 8-12 48-Pin Dual-In-Line Package (Plastic) ............................................................ 9-1 52-Lead QUAD Package ................................................................................. 9-2 Case 767-02-P Suffix ..................................................................................... 9-2 Case 778-02-FN Suffix ................................................................................... 9-3
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LIST OF TABLES
Table Number 1-1. 2-1. Title Page Number
MFP Register Map ......................................................................................... 1-2 Signal Summary ............................................................................................. 2-5
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SECTION 1 INTRODUCTION
The MC68HC901 Multi-Function Peripheral (MFP) is a member of the M68000 Family of peripherals. Unless otherwise specified, the MC68HC901 multi-function peripheral is hereafter referred to as the MFP in this document. Many features of the MFP make reference to the MC68000 Family of 16- and 32-bit microprocessors, which includes the MC68HC000, MC68HC001, and the MC68EC000. These microprocessors are referred to as the MC68000 within this document. The MFP directly interfaces to the MC68000 via the asynchronous bus structure. Both vectored and polled interrupt schemes are supported with the MFP providing unique vector number generation for each of its 16 interrupt sources. Additionally, handshake lines are provided to facilitate direct memory access controller (DMAC) interfacing. Refer to Figure 1-1 for a block diagram of the MFP.
CLK RESET VCC GND
INTERNAL CONTROL LOGIC TIMERS C&D TCO TDO XTAL1 XTAL2 TIMERS A&B TAO TAI TBO TBI RR SI RC SO TC TR
D0 - D7
RS1 - RS5 CS R/W DS DTACK
CPU BUS I/O
USART
GENERAL PURPOSE I / O INTERRUPTS
I0 - I7
INTERRUPT CONTROL
IRQ
IEI
IEO
IACK
Figure 1-1. MFP Block Diagram
MOTOROLA MC68HC901 USER'S MANUAL FIGURE - MFP BLOCK DIAGRAM
MC68HC901UM / AD
1-1
Introduction
1.1 KEY FEATURES
The MFP performs many of the functions common to most microprocessor-based systems. The resources available to the user include: * Eight individually programmable I/O pins with interrupt capability * 16-source interrupt controller with individual source enable and masking * Four timers, two of which are multi-mode timers * Single-channel full-duplex universal synchronous/asynchronous receiver-transmitter (USART) which supports: -- asynchronous formats -- byte synchronous formats, with the addition of a polynomial generator checker By incorporating multiple functions within the MFP, the system designer retains flexibility while minimizing device count.
1.2 REGISTER PROGRAMMING
From a programmer's point of view, the versatility of the MFP may be attributed to its register set. The registers are well organized and allow the MFP to be easily tailored to a variety of applications. All of the 24 registers are also directly addressable which simplifies programming. The register map is shown in Table 1-1. Table 1-1. MFP Register Map
ADDRESS HEX RS5 01 03 05 07 09 0B 0D 0F 11 13 15 0 0 0 0 0 0 0 0 0 0 0 RS4 0 0 0 0 0 0 0 0 1 1 1 BINARY RS3 0 0 0 0 1 1 1 1 0 0 0 RS2 0 0 1 1 0 0 1 1 0 0 1 RS1 0 1 0 1 0 1 0 1 0 1 0 GPDR AER DDR IERA IERB IPRA IPRB ISRA ISRB IMRA IMRB General Purpose I / O Data Register Active Edge Register Data Direction Register Interrupt Enable Register A Interrupt Enable Register B Interrupt Pending Register A Interrupt Pending Register B Interrupt In-service Register A Interrupt In-service Register B Interrupt Mask Register A Interrupt Mask Register B ABBREVIATION REGISTER NAME
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Table 1-1. MFP Register Map (Continued)
ADDRESS HEX RS5 17 19 1B 1D 1F 21 23 25 27 29 2B 2D 2F 0 0 0 0 0 1 1 1 1 1 1 1 1 RS4 1 1 1 1 1 0 0 0 0 0 0 0 0 BINARY RS3 0 1 1 1 1 0 0 0 0 1 1 1 1 RS2 1 0 0 1 1 0 0 1 1 0 0 1 1 RS1 1 0 1 0 1 0 1 0 1 0 1 0 1 VR TACR TBCR TCDCR TADR TBDR TCDR TDCR SCR UCR RSR TSR UDR Vector Register Timer A Control Register Timer B Control Register Timers C and D Control Register Timer A Data Register Timer B Data Register Timer C Data Register Timer D Data Register Synchronous Character Register USART Control Register Receiver Status Register Transmitter Status Register USART Data Register ABBREVIATION REGISTER NAME
NOTE: Hex addresses assume that RS1 connects with A1, RS2 connects with A2, etc., and that DS is connected to LDS on the MC68000 or DS is connected to DS on the MC68008.
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SECTION 2 SIGNAL DESCRIPTION
This section contains descriptions of the input and output signals. The input and output signals can be functionally organized into groups as shown in Figure 2-1. The following paragraphs provide a brief description of the signal and a reference (if applicable) to other sections that contain more detail about its function. NOTE
Assertion and negation are used to specify forcing a signal to a particular state. Assertion and assert refer to a signal that is active or true. Negation and negate refer to a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent.
POWER SUPPLY
VCC GND CLK D0 - D7 CS DS R/W DTACK RS1 - RS5 RESET REG SEL DATA BUS MC68HC901 MULTI-FUNCTION PERIPHERAL (MFP)
GPIP
I0 - I7 TAI TBI TAO TBO TCO TDO XTAL1 XTAL2 SI SO RC TC RR TR
TIMER CONTROL
ASYNCHRONOUS BUS CONTROL
SERIAL I / O CONTROL
INTERRUPT CONTROL
IRQ IACK IEI IEO
DMA CONTROL
Figure 2-1. Input and Output Signals
2.1 POWER SUPPLY (VCC and GND) OUTPUT SIGNALS FIGURE - INPUT AND
Power is supplied to the MFP using theseMC68HC901UM / AD The VCC pin is powered at +5 volts, connections. and ground is connected to the GND pins.
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Signal Description
2.2 CLOCK (CLK)
The clock input is a single-phase TTL-compatible signal used for internal timing. This input must conform to minimum pulse width times. The clock is not necessarily the system clock in frequency or phase.
2.3 DATA BUS (D7-D0)
This three-state bidirectional bus is used to transmit data to or receive data from the MFP internal registers during a processor read or write cycle, respectively. During an interrupt acknowledge cycle, the data bus is used to pass a vector number to the processor. The MFP must be located on data bus lines D7-D0 when used with either the MC68000 series of microprocessors and on data lines D31-D24 when used with the MC68020 microprocessor, if vectored interrupts are to be used.
2.4 ASYNCHRONOUS BUS CONTROL
Asynchronous data transfers are controlled by chip select, data strobe, read/write, and data transfer acknowledge. The register select lines, RS5-RS1, select an internal MFP register for a read or write operation. The reset line initializes the MFP registers and the internal control signals.
2.4.1 Chip Select (CS)
This active low input activates the MFP for internal register access. CS and IACK must not be asserted at the same time.
2.4.2 Data Strobe (DS)
This active low input is part of the internal chip select and interrupt acknowledge functions.
2.4.3 Read/Write (R/W)
This input defines the current bus cycle as a read (high) or a write (low) cycle.
2.4.4 Data Transfer Acknowledge (DTACK)
This active low, three-state output signals the completion of the operation phase of a bus cycle to the processor. If the bus cycle is a process read, the MFP asserts DTACK to indicate that the information on the data bus is valid. If the bus cycle is a processor write to the MFP, DTACK acknowledges the acceptance of the data by the MFP. DTACK will be asserted only by a MFP that has CS or IACK (and IEI) asserted.
2.5 REGISTER SELECT BUS (RS1-RS5)
The register select bus selects an internal MFP register during a read or write operation.
2.6 RESET (RESET)
This active low input will initialize the MFP during powerup or in response to a total system reset. Refer to Section 3.3 Reset Operation for further information.
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Signal Description
2.7 INTERRUPT CONTROL
The interrupt request and interrupt acknowledge signals are handshake lines for a vectored interrupt scheme. Interrupt enable in and interrupt enable out implement a daisy-chained interrupt structure.
2.7.1 Interrupt Request (IRQ)
This active low, open-drain output signals to the processor that an interrupt is pending from the MFP. There are 16 interrupt channels that can generate an interrupt request. Clearing the interrupt pending registers (IPRA and IPRB) or clearing the interrupt mask registers (IMRA and IMRB) will cause the IRQ to be negated. IRQ will also be negated as the result of an interrupt acknowledge cycle, unless additional interrupts are pending in the MFP. Refer to Section 4 Interrupt Structure for further information.
2.7.2 Interrupt Acknowledge (IACK)
If both IRQ and IEI are asserted, the MFP will begin an interrupt acknowledge cycle when IACK and DS are asserted. The MFP will supply a unique vector number to the processor which corresponds to the particular channel requesting interrupt service. In a daisy-chained interrupt structure, all devices in the chain must have a common IACK. Refer to Section 3.2 Interrupt Acknowledge Operation and Section 4.1.2 Interrupt Vector Number for additional information. CS and IACK must not be asserted at the same time.
2.7.3 Interrupt Enable In (IEI)
This active low input, together with the IEO signal, provides a daisy-chained interrupt structure for a vectored interrupt scheme. IEI indicates that no higher priority device is requesting interrupt service. So, the highest priority MFP in the chain should have its IEI pin tied low. During an interrupt acknowledge cycle, a MFP with a pending interrupt is not allowed to pass a vector number to the processor until its IEI pin is asserted. When the daisy-chain option is not implemented, all MFPs should have their IEI pin tied low. Refer to Section 4.2 Daisy-Chaining MFPs for additional information.
2.7.4 Interrupt Enable Out (IEO)
This active low output, together with the IEI signal, provides a daisy-chained interrupt structure for a vectored interrupt scheme. The IEO of a particular MFP signals lower priority devices that neither it nor any other higher priority device is requesting interrupt service. When a daisy-chain is implemented, IEO is tied to the next lower priority MFP IEI input. The lowest priority MFP is not connected. When the daisy-chain option is not implemented, IEO is not connected. Refer to Section 4.2 Daisy-Chaining MFPs for additional information.
2.8 GENERAL PURPOSE I/O INTERRUPT LINES (I7-I0)
These lines constitute an 8-bit pin-programmable I/O port with interrupt capability. The data direction register (DDR) individually defines each line as either a high-impedance input or a TTL-compatible output. As an input, each line can generate an interrupt on the user selected transition of the input signal. Refer to Section 5 General Purpose Input/Output Port for further information.
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Signal Description
2.9 TIMER CONTROL
These lines provide internal timing and auxiliary timer control inputs required for certain operating modes. Additionally, the timer outputs are included in this group.
2.9.1 Timer Inputs (TAI and TBI)
These input lines are control signals for timers A and B in the pulse width measurement mode and the event count mode. These signals generate interrupts at the same priority level as the general purpose I/O interrupt lines I4 and I3, respectively, when in the pulse width measurement mode. While I4 and I3 do not have interrupt capability when timers A and B are operated in this mode, they may still be used for I/O. Refer to Section 6.1.2 Pulse Width Measurement Mode Operation and Section 6.1.3 Event Count Mode Operation for further information.
2.9.2 Timer Outputs (TAO, TBO, TCO, and TDO)
Each timer has an associated output which toggles when its main counter counts through 01 (hexadecimal) regardless of which operational mode is selected. When in the delay mode, the timer output will be a square wave with a period equal to two timer cycles. This output may be used to supply the universal synchronous/asynchronous receiver-transmitter (USART) baud rate clocks.
2.9.3 Timer Clock (XTAL1 and XTAL2)
These pins provide the timing signal for the four timers. A crystal can be connected between the timer clock pins, XTAL1 and XTAL2, or XTAL1 can be driven with a CMOS-level clock while XTAL2 is not connected. The following crystal parameters are suggested: 1. Parallel resonance, fundamental mode AT-cut, HC6 or HC33 holder 2. Frequency tolerance measured with 18 picofarads load (0.1% accuracy) - drive level 10 microwatts 3. Shunt capacitance equals 7 picofarads 4. Series resistance: 2.0 < f < 2.7 MHz; Rs 300 ohms 2.8 < f < 4.0 MHz; Rs 150 ohms
2.10 SERIAL I/O CONTROL
The full duplex serial channel is implemented by a serial input line. The independent receive and transmit sections may be clocked by separate timing signals on the receive clock input and the transmitter clock input.
2.10.1 Serial Input (SI)
This input line is the USART receiver data input. This input is not used in the USART loopback mode. Refer to Section 7.3.2 Transmitter Status Register for additional information.
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2.10.2 Serial Output (SO)
This output line is the USART transmitter data output. This output is in a high-impedance state after a device reset.
2.10.3 Receiver Clock (RC)
This input controls the serial bit rate of the receiver. The signal may be supplied by the timer output lines or by an external TTL-level clock which meets the minimum and maximum cycle times. This clock is not used in the USART loopback mode. Refer to Section 7.3.2 Transmitter Status Register for additional information.
2.10.4 Transmitter Clock (TC)
This input controls the serial bit rate of the transmitter. This signal may be supplied by the timer output lines or by an external TTL-level clock which meets the minimum and maximum cycle times.
2.11 DIRECT MEMORY ACCESS CONTROL
The USART section of the MFP supports direct memory access transfers through its receiver ready and transmitter ready status lines.
2.11.1 Receiver Ready (RR)
This active low output reflects the receiver buffer full status (bit 7 in the Receiver Status Register) for DMA operations.
2.11.2 Transmitter Ready (TR)
This active low output reflects the transmitter buffer empty (bit 7 in the Transmitter Status Register) for DMA operations.
2.12 SIGNAL SUMMARY
The following table is a summary of all the signals discussed in the previous paragraphs. Table 2-1. Signal Summary
SIGNAL NAME Power Input Ground Clock Chip Select Data Strobe Read / Write MNEMONIC VCC GND CLK CS DS R/W INPUT/ OUTPUT Input Input Input Input Input Input ACTIVE STATE High Low N/A Low Low Read - High, Write - Low THREESTATE -- -- RESET STATE -- --
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Table 2-1. Signal Summary (Continued)
SIGNAL NAME Data Transfer Acknowledge Register Select Bus Data Bus MNEMONIC DTACK RS1 - RS5 D0 - D7 INPUT/ OUTPUT Output Input Input / Output Input Output Input Input Output Input / Output Input Output Input Output ACTIVE STATE Low N/A N/A Yes Hi-z THREESTATE Yes RESET STATE High
Reset Interrupt Request Interrupt Acknowledge Interrupt Enable In Interrupt Enable Out General Purpose I / O Timer Clock
RESET IRQ IACK IEI IEO I0 - I7 XTAL1 XTAL2
Low Low Low Low Low N/A N/A N/A N/A N/A No Low No No Yes High Hi-Z No* High
Timer Inputs Timer Outputs
TAI, TBI TAO, TBO, TCO, TDO SI SO RC TC RR TR
Serial Input Serial Output Receiver Clock Transmitter Clock Receiver Ready Transmitter Ready * Open Drain
Input Output Input Input Output Output
N/A N/A N/A N/A Low Low No No High Low Yes Hi-Z
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SECTION 3 BUS OPERATION
The following paragraphs describe control signals and the bus operation during data transfer, interrupt acknowledge, and reset operations.
3.1 DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following pins: * Register Select Bus - RS1 through RS5 * Data Bus - D0 through D7 * Control Signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cases, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. Additionally, the bus master is responsible for deskewing the acknowledge and data signals from the peripheral devices.
3.1.1 Read Cycle
To read an MFP register, CS and DS must be asserted, and R/W must be high. The MFP will place the contents of the register which is selected by the register select bus (RS1 through RS5) on the data bus (D0 through D7) and then assert DTACK. The register addresses are shown in Table 1-1. After the processor has latched the data, it negates DS. The negation of either CS or DS will terminate the read operation. The MFP will drive DTACK high and place it and the data bus in the high-impedance state. The timing for a read cycle is shown in Figure 3-1. Refer to Section 8.7 AC Electrical Characteristics for actual timing numbers.
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CLK R/W CS DS RS1 - RS5 D0 - D7 DTACK
Figure 3-1. Read Cycle Timing Diagram
3.1.2 Write Cycle
To write a register, CS and DS must be asserted, and R/W must be low. The MFP will MC68HC901UM / AD decode the address bus to determine which register is selected. Then the register will be loaded with the contents of the data bus on the next valid falling edge of CLK, and DTACK will be asserted. When the processor recognizes DTACK, it will negate DS. The write cycle is terminated when either CS or DS is negated. The MFP will drive DTACK high and place it in the high-impedance state. The timing for a write cycle is shown in Figure 3-2. Refer to Section 8.7 AC Electrical Characteristics for actual timing numbers.
CLK R/W CS DS RS1 - RS5 D0 - D7 DTACK FIGURE - READ CYCLE TIMING DIAGRAM
Figure 3-2. Write Cycle Timing Diagram
3.2 INTERRUPT ACKNOWLEDGE OPERATION
The MFP has 16 interrupt sources: eight MC68HC901UM / AD eight external. When an interrupt internal and request is pending, the MFP will assert IRQ. In a vectored interrupt scheme, the processor will acknowledge the interrupt request by performing an interrupt acknowledge cycle. IACK and DS will be asserted. The MFP responds to the IACK signal by placing a vector number on the data bus. This vector number corresponds to the particular interrupt channel requesting service. The format of this vector number is further discussed in Section 4.1.2 Interrupt Vector Number.
FIGURE - WRITE CYCLE TIMING DIAGRAM
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Bus Operation
When the MFP asserts DTACK to indicate that valid data is on the bus, the processor will latch the data and terminate the bus cycle by negating DS. When either DS or IACK is negated, the MFP will terminate the interrupt acknowledge operation by driving DTACK high and placing it in the high-impedance state. IRQ will be negated as a result of the IACK cycle unless additional interrupts are pending. The MFP can be part of a daisy-chain interrupt structure which allows multiple MFPs to be placed at the same interrupt level by sharing a common IACK signal. A daisy-chain priority scheme is implemented with signals IEI and IEO. IEI indicates that no higher priority device is requesting interrupt service. IEO signals lower priority devices that neither this device nor any higher priority MFP is requesting service. To daisy-chain MFPs, the highest priority MFP has its IEI tied low and successive MFPs have their IEI connected to the next higher priority MFPs IEO. When the daisy-chain interrupt structure is not implemented, the IEIs of all MFPs must be tied low and the IEOs left unconnected. Refer to Section 4.2 Daisy-Chaining MFPs for additional information. When the processor initiates an interrupt acknowledge cycle by driving IACK and DS, the MFP, whose IEI is low, may respond with a vector number if an interrupt is pending. If this device does not have a pending interrupt, IEO is asserted which allows the next lower priority device to respond to the interrupt acknowledge. When an MFP propagates IEO, it will not drive the data bus nor DTACK during the interrupt acknowledge cycle. The timing for an IACK cycle is shown in Figure 3-3. Refer to Section 8.7 AC Electrical Characteristics and Figures 7-7 and 7-8 for further information.
CLK IACK DS IEI IEO D0 - D7 DTACK
Figure 3-3. IACK Cycle Timing Diagram
3.3 RESET OPERATION
The reset operation will initialize the MFP to a knownAD MC68HC901UM / state. The reset operation requires that the RESET input be asserted for a minimum of two microseconds. During a device reset condition, all internal MFP registers are cleared except for the timer data registers (TADR, TBDR, TCDR, and TDDR), the USART data register (UDR), and the transmitter status register (TSR). All timers are stopped, the USART receiver and transmitter are disabled, and the serial output (SO) line is placed in high impedance. The interrupt channels are also disabled and any pending interrupts are cleared. In addition, the general purpose interrupt
FIGURE - IACK CYCLE TIMING DIAGRAM
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I/O lines are placed in the high-impedance input mode, and the timer outputs are driven low. External MFP signals are negated. Since the vector register (VR) is initialized to a $00, an uninitialized MFP may not respond to an interrupt acknowledge cycle with the uninitialized interrupt vector, $0F. Refer to Section 4.1.2 Interrupt Vector Number for more information.
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SECTION 4 INTERRUPT STRUCTURE
In an M68000 system, the MFP will be assigned to one of the seven possible interrupt levels. All interrupt service requests from the MFP 16 interrupt channels will be presented at this level. As an interrupt controller, the MFP will internally prioritize its 16 interrupt sources. Additional interrupt sources may be placed at the same interrupt level by daisy-chaining multiple MFPs. The MFPs will be prioritized by their position in the chain.
4.1 INTERRUPT PROCESSING
Each MFP provides individual interrupt capability for its various functions. When an interrupt is received on one of the external interrupt channels or from one of the eight internal sources, the MFP will request interrupt service. The 16 interrupt channels are assigned a fixed priority so that multiple pending interrupts are serviced according to their relative importance. Since the MFP can internally generate 16 vector numbers, the unique vector number which corresponds to the highest priority channel that has a pending interrupt is presented to the processor during an interrupt acknowledge cycle. This unique vector number allows the processor to immediately begin execution of the interrupt handler for the interrupting source, decreasing interrupt latency.
4.1.1 Interrupt Channel Prioritization
The 16 interrupt channels are prioritized from highest to lowest, with General Purpose Interrupt 7 (I7) being the highest and I0 the lowest. The priority of the interrupt is determined by the least-significant four bits in the interrupt vector number which are internally generated by the MFP. Pending interrupts are presented to the processor in order of priority unless they have been masked. By selectively masking interrupts, the channels are in effect re-prioritized.
4.1.2 Interrupt Vector Number
During an interrupt acknowledge cycle, a unique 8-bit interrupt vector number is presented to the system which corresponds to the specific interrupt source that is requesting service.
BIT FIELD 7 V7 6 V6 5 V5 4 V4 3 IV3 2 IV2 1 IV1 0 IV0
V7-V4 -- Vector The four most significant bits are copied from the vector register.
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IV3-IV0 -- Interrupt Vector These bits are supplied by the MFP. They are the binary channel number of the highest priority channel that is requesting interrupt service.
IV3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
IV2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
IV1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
IV0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
DESCRIPTION General Purpose Interrupt 7 (I7) General Purpose Interrupt 6 (I6) Timer A Receiver Buffer Full Receive Error Transmit Buffer Empty Transmit Error Timer B General Purpose Interrupt 5 (I5) General Purpose Interrupt 4(I4) Timer C Timer D General Purpose Interrupt 3 (I3) General Purpose Interrupt 2 (I2) General Purpose Interrupt 1 (I1) General Purpose Interrupt 0 (I0)
4.1.3 Vector Register (VR)
This 8-bit register determines the four most-significant bits in the interrupt vector format and which end-of-interrupt mode is used in a vectored interrupt scheme. The vector register should be written to before writing to the interrupt mask or enable registers to ensure that the MFP responds to an interrupt acknowledge cycle with a vector number not in the range of allowable user vectors. For information refer to Section 4.4.1 Selecting the End-OfInterrupt Mode.
VR REGISTER BIT FIELD RESET ADDR 7 V7 0 6 V6 0 5 V5 0 4 V4 0 $17 3 S 0 2 * 0 1 * 0 0 * 0
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V7-V4 -- Vector These upper four bits of the vector register are written by the user. These bits become the most-significant four bits of the interrupt vector number. S -- In-Service Register Enable 1 = Software end-of-interrupt mode and in-service register bits enabled. 0 = Automatic end-of-interrupt mode and in-service register bits forced low. Bits 2-0 -- *Unused Unused bits read as zero.
4.2 DAISY-CHAINING MFPs
As an interrupt controller, the MFP will support eight external interrupt sources in addition to its eight internal interrupt sources. When a system requires more than eight external interrupt sources to be placed at the same interrupt level, sources may be added to the prioritized structure by daisy-chaining MFPs. Interrupt sources are prioritized internally within each MFP, and the MFPs are prioritized by their position in the chain. Unique vector numbers are provided for each interrupt source. The IEI and IEO signals implement the daisy-chained structure. The IEI of the highest priority MFP is tied low and the IEO output of this device is tied to the next highest priority MFP IEI. The IEI and IEO signals are daisy-chained in this manner for all the MFPs in the chain with the lowest priority MFP IEO left unconnected. Figure 4-1 shows a diagram of the interrupt daisy-chain. Daisy-chaining requires that all parts in the chain have a common IACK. When the common IACK is asserted during an interrupt acknowledge cycle, all parts will prioritize interrupts in parallel. When the IEI signal to an MFP is asserted, the part may respond to the IACK cycle if it requires interrupt service. Otherwise, the part will assert IEO to the next lower priority device. Thus, priority is passed down the chain via IEI and IEO until a part which has a pending interrupt is reached. The part with the pending interrupt passes a vector number to the processor and does not propagate IEO.
HIGHEST PRIORITY MC68HC901 MC68HC901 LOWEST PRIORITY MC68HC901
IEI
IEO
IEI
IEO
IEI
IACK IACK
IACK
IACK
Figure 4-1. Daisy-Chained Interrupt Structure
FIGURE - DAISY-CHAINED INTERRUPT STRUCTURE MC68HC901UM / AD
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4.3 INTERRUPT CONTROL REGISTERS
MFP interrupt processing is managed by the enable registers A and B, interrupt pending registers A and B, and interrupt mask registers A and B. These registers allow the programmer to enable or disable individual interrupt channels, mask individual interrupt channels, and access pending interrupt status information. In-service registers A and B allow interrupts to be nested as described in Section 4.4 Nesting MFP Interrupts. The interrupt control registers are shown in the following paragraphs.
4.3.1 Interrupt Enable Registers (IERA, IERB)
The interrupt channels are individually enabled or disabled by writing a one or a zero, respectively, to the appropriate bit of interrupt enable register A or B (IERA or IERB). The processor may read these registers at any time. When a channel is enabled, interrupts received on the channel will be recognized by the MFP, and IRQ will be asserted to the processor indicating that interrupt service is required. On the other hand, a disabled channel is completely inactive; interrupts received on the channel are ignored by the MFP. Writing a zero to a bit of interrupt enable register A or B will cause the corresponding bit of the interrupt pending register to be cleared. This will terminate all interrupt service requests for the channel and also negate IRQ unless interrupts are pending from other sources. Disabling a channel, however, does not affect the corresponding bit in interrupt in-service registers A or B. So, if the MFP is in the software end-of-interrupt mode (refer to Section 4.4.3 Software End-Of-Interrupt Mode) and an interrupt is in service when a channel is disabled, the in-service bit of that channel will remain set until cleared by software.
IERA REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 TIMER A 0 4 RCV BUFFER FULL 0 $07 3 RCV ERROR 0 2 XMIT BUFFER EMPTY 0 1 XMIT ERROR 0 0 TIMER B 0
GPIP7-GPIP6 -- General Purpose Interrupt Enable 1 = Enable. 0 = Disable. Timer A -- Timer A Interrupt Enable 1 = Enable. 0 = Disable. Receiver Buffer Full -- Receiver Buffer Full Interrupt Enable 1 = Enable. 0 = Disable.
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Receiver Error -- Receiver Buffer Full Interrupt Enable 1 = Enable. 0 = Disable. Transmitter Buffer Empty -- Transmitter Buffer Interrupt Enable 1 = Enable. 0 = Disable. Transmitter Error -- Transmitter Error Interrupt Enable 1 = Enable. 0 = Disable. Timer B -- Timer B Interrupt Enable 1 = Enable. 0 = Disable.
IERB REGISTER BIT FIELD RESET ADDR 7 GPIP5 0 6 GPIP4 0 5 TIMER C 0 4 TIMER D 0 $09 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP5-GPIP4 -- General Purpose Interrupt Enable 1 = Enable. 0 = Disable. Timer C -- Timer C Interrupt Enable 1 = Enable. 0 = Disable. Timer D -- Timer D Interrupt Enable 1 = Enable. 0 = Disable. GPIP3-GPIP0 -- General Purpose Interrupt Enable 1 = Enable. 0 = Disable.
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4.3.2 Interrupt Pending Registers (IPRA, IPRB)
When an interrupt is received on an enabled channel, the corresponding interrupt pending bit is set in interrupt pending register A or B (IPRA or IPRB). In a vectored interrupt scheme, this bit will be cleared when the processor acknowledges the interrupting channel and the MFP responds with a vector number. In a polled interrupt system, the interrupt pending registers must be read to determine the interrupting channel, and then the interrupt pending bit is cleared by the interrupt handling routine without performing an interrupt acknowledge sequence.
IPRA REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 TIMER A 0 4 RCV BUFFER FULL 0 $0B 3 RCV ERROR 0 2 XMIT BUFFER EMPTY 0 1 XMIT ERROR 0 0 TIMER B 0
GPIP7-GPIP6 -- General Purpose Interrupt Pending 1 = Pending. 0 = Cleared. Timer A -- Timer A Interrupt Pending 1 = Pending. 0 = Cleared. Receiver Buffer Full -- Receiver Buffer Full Interrupt Pending 1 = Pending. 0 = Cleared. Receiver Error -- Receiver Buffer Full Interrupt Pending 1 = Pending. 0 = Cleared. Transmitter Buffer Empty -- Transmitter Buffer Interrupt Pending 1 = Pending. 0 = Cleared. Transmitter Error -- Transmitter Error Interrupt Pending 1 = Pending. 0 = Cleared. Timer B -- Timer B Interrupt Pending 1 = Pending. 0 = Cleared.
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IPRB REGISTER BIT FIELD RESET ADDR 7 GPIP5 0 6 GPIP4 0 5 TIMER C 0 4 TIMER D 0 $0D 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP5-GPIP4 -- General Purpose Interrupt Pending 1 = Pending. 0 = Cleared. Timer C -- Timer C Interrupt Pending 1 = Pending. 0 = Cleared. Timer D -- Timer D Interrupt Pending 1 = Pending. 0 = Cleared. GPIP3-GPIP0 -- General Purpose Interrupt Pending 1 = Pending. 0 = Cleared.
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4.3.3 Interrupt Mask Registers (IMRA, IMRB)
Interrupts are masked for a channel by clearing the appropriate bit in interrupt mask register A or B (IMRA or IMRB). Even though an enabled channel is masked, the channel will recognize subsequent interrupts and set its interrupt pending bit. However, the channel is prevented from requesting interrupt service (IRQ to the processor) as long as the mask bit for that channel is cleared. If a channel is requesting interrupt service at the time that its corresponding bit in IMRA or IMRB is cleared, the request will cease, and IRQ will be negated unless another channel is requesting interrupt service. Later, when the mask bit is set, any pending interrupt on the channel will be processed according to the channel's assigned priority. IMRA and IMRB may be read at any time. Figure 4-2 provides a conceptual circuit of an MFP interrupt channel.
IMRA REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 TIMER A 0 4 RCV BUFFER FULL 0 $13 3 RCV ERROR 0 2 XMIT BUFFER EMPTY 0 1 XMIT ERROR 0 0 TIMER B 0
GPIP7-GPIP6 -- General Purpose Interrupt Mask 1 = Unmask. 0 = Mask. Timer A -- Timer A Interrupt Mask 1 = Unmask. 0 = Mask. Receiver Buffer Full -- Receiver Buffer Full Interrupt Mask 1 = Unmask. 0 = Mask. Receiver Error -- Receiver Buffer Full Interrupt Mask 1 = Unmask. 0 = Mask. Transmitter Buffer Empty -- Transmitter Buffer Interrupt Mask 1 = Unmask. 0 = Mask. Transmitter Error -- Transmitter Error Interrupt Mask 1 = Unmask. 0 = Mask.
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Timer B -- Timer B Interrupt Mask 1 = Unmask. 0 = Mask.
IMRB REGISTER BIT FIELD RESET ADDR 7 GPIP5 0 6 GPIP4 0 5 TIMER C 0 4 TIMER D 0 $15 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP5-GPIP4 -- General Purpose Interrupt Mask 1 = Unmask. 0 = Mask. Timer C -- Timer C Interrupt Mask 1 = Unmask. 0 = Mask. Timer D -- Timer D Interrupt Mask 1 = Unmask. 0 = Mask. GPIP3-GPIP0 -- General Purpose Interrupt Mask 1 = Unmask. 0 = Mask.
EDGE REGISTER
ENABLE REGISTER
MASK REGISTER
S-BIT
S 17
INTERRUPT Q PENDING R
S
INTERRUPT IN-SERVICE
INTERRUPT REQUEST
PASS VECTOR
Figure 4-2. Conceptual Circuits of an Interrupt Channel
FIGURE - CONCEPTUAL CIRCUITS OF AN INTERRUPT CHANNEL MC68HC901UM / AD
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4.3.4 Interrupt In-Service Registers (ISRA, ISRB)
These registers indicate whether interrupt processing is in progress for a certain channel. A bit is set whenever an interrupt vector number is passed for a interrupt channel during an IACK cycle and the S bit of the vector register is a one. The bit is cleared whenever interrupt service is complete for an associated interrupt channel, the S bit of the vector register is cleared, or the processor writes a zero to the bit.
ISRA REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 TIMER A 0 4 RCV BUFFER FULL 0 $0F 3 RCV ERROR 0 2 XMIT BUFFER EMPTY 0 1 XMIT ERROR 0 0 TIMER B 0
GPIP7-GPIP6 -- General Purpose Interrupt Servicing 1 = In-service. 0 = No service in progress. Timer A -- Timer A Interrupt Servicing 1 = In-service. 0 = No service in progress. Receiver Buffer Full -- Receiver Buffer Full Interrupt Servicing 1 = In-service. 0 = No service in progress. Receiver Error -- Receiver Buffer Full Interrupt Servicing 1 = In-service. 0 = No service in progress. Transmitter Buffer Empty -- Transmitter Buffer Interrupt Servicing 1 = In-service. 0 = No service in progress. Transmitter Error -- Transmitter Error Interrupt Servicing 1 = In-service. 0 = No service in progress. Timer B -- Timer B Interrupt Servicing 1 = In-service. 0 = No service in progress.
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ISRB REGISTER BIT FIELD RESET ADDR 7 GPIP5 0 6 GPIP4 0 5 TIMER C 0 4 TIMER D 0 $11 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP5-GPIP4 -- General Purpose Interrupt Servicing 1 = In-service. 0 = No service in progress. Timer C -- Timer C Interrupt Servicing 1 = In-service. 0 = No service in progress. Timer D -- Timer D Interrupt Servicing 1 = In-service. 0 = No service in progress. GPIP3-GPIP0 -- General Purpose Interrupt Servicing 1 = In-service. 0 = No service in progress.
4.4 NESTING MFP INTERRUPTS
In an M68000 vectored interrupt system, the MFP is assigned to one of seven possible interrupt levels. When an interrupt is received from the MFP, an interrupt acknowledge for that level is initiated. Once an interrupt is recognized at a particular level, interrupts at the same level or below are masked by the processor. As long as the processor's interrupt mask is unchanged, the M68000 interrupt structure will prohibit nesting the interrupts at the same interrupt level. However, additional interrupt requests from the MFP can be recognized before a previous channel's interrupt service routine is finished by lowering the processor's interrupt mask to the next lower interrupt level within the interrupt handler. When nesting MFP interrupts, it may be desirable to permit interrupts on any MFP channel regardless of its priority, to pre-empt or delay interrupt processing of an earlier channel's interrupt service request. Or, it may be desirable to only allow subsequent higher priority channel interrupt requests to supercede previously recognized lower priority interrupt requests. The MFP interrupt structure provides the flexibility by offering two end-of-interrupt options for vectored interrupt schemes. The end-of-interrupt modes are not active in a polled interrupt scheme.
4.4.1 Selecting the End-Of-Interrupt Mode
In a vectored interrupt scheme, the MFP may be programmed to operate in either the automatic end-of-interrupt mode or the software end-of-interrupt mode. The mode is selected by writing the S bit of the vector register. When the S bit is programmed to a one,
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the MFP is placed in the software end-of-interrupt mode, and when the S bit is a zero, all channels operate in the automatic end-of-interrupt mode.
4.4.2 Automatic End-Of-Interrupt Mode
When an interrupt vector is passed to the processor during an interrupt acknowledge cycle, the corresponding channel's interrupt pending bit is cleared. In the automatic end-ofinterrupt mode, no further history of the interrupt remains in the MFP. The in-service bits of the interrupt in-service registers (ISRA and ISRB) are forced low. Subsequent interrupts, which are received on any MFP channel will generate an interrupt request to the processor even if the current interrupt's service routine has not been completed.
4.4.3 Software End-Of-Interrupt Mode
In the software end-of-interrupt mode, the channel's associated interrupt pending bit is cleared. In addition, the channel's in-service bit of in-service register A or B is set when its vector number is passed to the processor during the interrupt acknowledge cycle. A higher priority channel may subsequently request interrupt service and be acknowledged, but as long as the channel's in-service bit is set, no lower priority channel may request interrupt service nor pass its vector during an interrupt acknowledge sequence. While only higher priority channels may request interrupt service, any channel can receive an interrupt and set its interrupt pending bit. Even the channel with its in-service bit is set can receive a second interrupt. However, no interrupt service request is made until its in-service bit is cleared. The in-service bit for a particular channel can be cleared by writing a zero to its corresponding bit in ISRA or ISRB and ones to all other bit positions. Since bits in the in-service registers can only be cleared in software and not set, writing ones to the registers does not alter their contents. ISRA and ISRB may be read at any time.
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SECTION 5 GENERAL PURPOSE INPUT/OUTPUT PORT
The general purpose input/output (I/O) port (GPIP) provides eight I/O lines (I0 through I7) that may be operated as either inputs or outputs under software control. In addition, these lines may optionally generate an interrupt on either a positive transition or a negative transition of the input signal. The flexibility of the GPIP allows it to be configured as an 8-bit I/O port or for bit I/O. Since interrupts are enabled on a bit-by-bit basis, a subset of the GPIP could be programmed as handshake lines or the port could be connected to as many as eight external interrupt sources, which would be prioritized by the MFP interrupt controller for the interrupt service.
5.1 GPIP CONTROL REGISTERS
The GPIP is programmed via three control registers. These registers control the data direction, provide user access to the port, and specify the active edge for each bit of the GPIP which will produce an interrupt. These registers are described in detail in the following paragraphs.
5.1.1 General Purpose I/O Data Register (GPDR)
The general purpose I/O data register is used to input data from or output data to the port. When data is written to the GPDR, those pins which are defined as inputs will remain in the high-impedance state. Pins which are defined as outputs will assume the state (high or low) of their corresponding bit in the data register. When the GPDR is read, data will be passed directly from the bits of the data register for pins which are defined as outputs. Data from pins defined as inputs will come from the input buffers.
GPDR REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 GPIP5 0 4 GPIP4 0 $01 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP7-GPIP0 - General Purpose I/O Port 0 = Cleared. 1 = Set.
5.1.2 Active Edge Register (AER)
The active edge register (AER) allows each of the GPIP lines to produce an interrupt on either a one-to-zero or a zero-to-one transition. Writing a zero to the appropriate edge bit of
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the active edge register will cause the associated input to generate an interrupt on the oneto-zero transition. Writing a one to the edge bit will produce an interrupt on the zero-to-one transition of the corresponding line. When the processor sets a bit, interrupts will be generated on the rising edge of the associated input signal. When the processor clears a bit, interrupts will be generated on the falling edge of the associated input signal.
AER REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 GPIP5 0 4 GPIP4 0 $03 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP7-GPIP0 - General Purpose I/O Port 0 = Interrupts will be generated on the falling edge of the associated input signal. 1 = Interrupts will be generated on the rising edge of the associated input signal. NOTE The inputs to the exclusive-OR of the transition detector are the edge bit and the input buffer. As a result, writing the AER may cause an interrupt-producing transition, depending upon the state of the input. So, the AER should be configured before enabling interrupts via the interrupt enable registers (IERA and IERB). Also, changing the edge bit while interrupts are enabled may cause an interrupt on the corresponding channel.
5.1.3 Data Direction Register (DDR)
The data direction register (DDR) allows the programmer to define I0 through I7 as inputs or outputs by writing the corresponding bit. When a bit of the data direction register is written as a zero, the corresponding interrupt I/O pin will be a high-impedance input. Writing a one to any bit of the data direction register will cause the corresponding pin to be configured as a push-pull output.
DDR REGISTER BIT FIELD RESET ADDR 7 GPIP7 0 6 GPIP6 0 5 GPIP5 0 4 GPIP4 0 $05 3 GPIP3 0 2 GPIP2 0 1 GPIP1 0 0 GPIP0 0
GPIP7-GPIP0 - General Purpose I/O Port 0 = Associated I/O line is defined to be an input. 1 = Associated I/O line is defined to be an output.
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SECTION 6 TIMERS
The MFP contains four 8-bit timers which provide many functions typically required in microprocessor systems. The timers can supply the baud rate clocks for the on-chip serial I/O channel, generate periodic interrupts, measure elapsed time, and count signal transitions. In addition, two timers have waveform generation capability. All timers are prescaler/counter timers with a common independent clock input (XTAL1 and XTAL2). Each timer's output signal toggles when the timer's main counter times out. Additionally, timers A and B have auxiliary control signals (TAI, TBI) which are used in two of the operation modes. An interrupt channel is assigned to each timer, and when the auxiliary control signals are used in the pulse width measurement mode, a separate interrupt channel will respond to transitions on these inputs.
6.1 OPERATION MODES
Timers A and B are full function timers which, in addition to the delay mode, operate in the pulse width measurements mode and the event count mode. Timers C and D are delay timers only. A brief discussion of each of the timer modes follows.
6.1.1 Delay Mode Operation
All timers may operate in the delay mode. In this mode, the prescaler is always active. The prescaler specifies the number of timer clock cycles which must elapse before a count pulse is applied to the main counter. A count pulse causes the main counter to decrement by one. When the timer has decremented down to 01 (hexadecimal), the next count pulse will cause the main counter to be reloaded from the timer data register and a time out pulse will be produced. This time out pulse is coupled to the timer's interrupt channel and, if the channel is enabled, an interrupt will occur. The time out pulse also causes the timer output pin to toggle. The output will remain in this new state until the next time out pulse occurs. For example, if delay mode with a divide-by-10 prescaler is selected and the timer data register is loaded with 100 (decimal), the main counter will decrement once every 10 timer clock cycles. After 1000 timer clocks, a time out pulse will be produced. This time out pulse will generate an interrupt if the channel is enabled (IERA, IERB), and in addition, the timer's output line will toggle. The output line will complete one full period every 2000 cycles of the timer clock. If the prescaler value is changed while the timer is enabled, the first time out pulse will occur at an indeterminate time no less than one or more than 200 timer clock cycles. Subsequent time out pulses will then occur at the correct interval.
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If the main counter is loaded with 01 (hexadecimal), a time out pulse will occur every time the prescaler presents a count pulse to the main counter. If the main counter is loaded with 00, a time out pulse will occur every 256 count pulses.
6.1.2 Pulse Width Measurement Operation
Besides the delay mode, timers A and B may be programmed to operate in the pulse width measurement mode. In this mode, an auxiliary control input is required; timers A and B auxiliary input lines are TAI and TBI. Also, in the pulse width measurement mode, interrupt channels normally associated with I4 and I3 will instead respond to transitions on TAI and TBI, respectively. General purpose lines I3 and I4 may still be used for I/O, but may not be used as interrupt generating inputs. A conceptual circuit of the selection of the interrupt source is shown in Figure 6-1.
TAI
TIMER A PULSE- WIDTH MODE
INTERRUPT CHANNEL 14 (0110)
13 INTERRUPT CHANNEL (0011)
TIMER B PULSE- WIDTH MODE
TBI
Figure 6-1. Conceptual Circuit of Interrupt Source Selection The pulse width measurement mode functions similarly to the delay mode, with the auxiliary FIGURE - CONCEPTUAL CIRCUIT OF When SOURCE SELECTION control signal acting as an enable to the timer. INTERRUPTthe control signal is active, the MC68HC901UM / AD prescaler and main counter are allowed to operate. When the control signal is negated, the timer is stopped. So, the width of the active pulse on TAI or TBI is measured by the number of timer counts which occur while the timer is allowed to operate. The active state of the auxiliary input line is defined by the associated interrupt channel's edge bit in the active edge register (AER). GPIP4 of the AER is the edge bit associated with TAI, and GPIP3 is associated with TBI. When the edge bit is a one, the auxiliary input will be active high, enabling the timer while the input signal is at a high level. If the edge bit is zero, the auxiliary input will be active low and the timer will operate while the input signal is at a low level.
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The state of the active edge bit also specifies whether a zero-to-one transition or a one-tozero transition of the auxiliary input pin will produce an interrupt when the interrupt channel is enabled. In normal operation, programming the active edge bit to a one will produce an interrupt on the zero-to-one transition of the associated input signal. Alternately, programming the edge bit to a zero will produce an interrupt on the one-to-zero transition of the input signal. However, in the pulse width measurement mode, the interrupt generated by a transition on TAI or TBI will occur on the opposite transition as that normally defined by the edge bit. For example, in the pulse width measurement mode, if the edge bit is a one, the timer will be allowed to run while the auxiliary input is high. When the input transitions from high to low, the timer will stop and, if the interrupt channel is enabled, an interrupt will occur. By having the interrupt occur on the one-to-zero transition instead of the zero-to-one transition, the processor will be interrupted when the pulse being measured has been terminated and the width of the pulse from the timer is available. After reading the contents of the timer, the processor must re-initialize the main counter by writing to the timer data register to allow consecutive pulses to be measured. If the data register is written after the auxiliary input signal becomes active, the timer will count from the previous contents of the timer data register until it counts through 01 (hexadecimal). At that time, the main counter is loaded with the new value from the timer data register, a time out pulse is generated which will toggle the timer output, and an interrupt may be optionally generated on the timer interrupt channel. Note that the pulse width measured includes counts from before the main counter was reloaded. If the timer data register is written while the pulse is transitioning to the active state, an indeterminate value may be written into the main counter. Once the timer is reprogrammed for another mode, interrupts will again occur as normally defined by the edge bit. Note that an interrupt may be generated as the result of placing the timer into the pulse width measurement mode or by reprogramming the timer for another mode. Also, an interrupt may be generated by changing the state of the edge bit while in the pulse width measurement mode.
6.1.3 Event Count Mode Operation
In addition to the delay mode and the pulse width measurement mode, timers A and B may be programmed to operate in the event count mode. Like the pulse width measurement mode, the event count mode requires an auxiliary input signal, TAI or TBI. General purpose lines I3 and I4 can be used for I/O or as interrupt producing inputs. In the event count mode, the prescaler is disabled allowing each active transition on TAI and TBI to produce a count pulse. The count pulse causes the main counter to decrement by one. When the timer counts through 01 (hexadecimal), a time out pulse is generated which will cause the output signal to toggle and may optionally produce an interrupt via the associated timer interrupt channel. The timer's main counter is also reloaded from the timer data register. To count transitions reliably, the input signal may only transition once every four timer clock periods. For this reason, the input signal must have a maximum frequency of one-fourth that of the timer clock.
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The active edge of the auxiliary input signal is defined by the associated channel's edge bit. GPIP4 of the AER specifies the active edge for TAI, and GPIP3 defines the active edge for TBI. When the edge bit is programmed to a one, a count pulse will be generated on the zeroto-one transition of the auxiliary input signal. When the edge bit is programmed to a zero, a count pulse will be generated on the one-to-zero transition. Also, note that changing the state of the edge bit while the timer is in the event count mode may produce a count pulse.
6.2 TIMER REGISTERS
The four timers are programmed via three control registers and four data registers. The following paragraphs describe the different registers.
6.2.1 Timer Data Registers (TxDR)
The four timer data registers (TDRs) are designated as Timer A data register (TADR), Timer B data register (TBDR), Timer C data register (TCDR), and Timer D data register (TDDR). Each timer's main counter is an 8-bit binary down counter. The timer data registers contain the value of their respective main counter. This value was captured on the last low-to-high transition of the data strobe pin. The main counter is initialized by writing to the TDR. If the timer is stopped, data is loaded simultaneously into both the TDR and main counter. If the TDR is written to while the timer is enabled, the value is not loaded into the timer until the timer counts through 01 (hexadecimal). If a write is performed while the timer is counting through 01, then an indeterminate value will be loaded into the timer's main counter.
TxDR REGISTER BIT FIELD RESET ADDR 7 D7 0 6 D6 0 5 D5 0 4 D4 0 3 D3 0 2 D2 0 1 D1 0 0 D0 0
$1F, $21, $23, $25
D7-D0 -- Data 0 = Cleared. 1 = Set.
6.2.2 Timer Control Registers (TxCR)
Timer A control register (TACR) and timer B control register (TBCR) are associated with timers A and B, respectively. Timers C and D are programmed using one control register-- the timer C and D control register (TCDCR). The bits in the control register select the operation mode, prescaler value, and disable the timers. Both control registers have bits which allow the programmer to reset output lines TA0 and TB0.
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TACR REGISTER BIT FIELD RESET ADDR TBCR REGISTER BIT FIELD RESET ADDR 7 * 0 6 * 0 5 * 0 4 RESET TBO 0 $1B 3 BC3 0 2 BC2 0 1 BC1 0 0 BC0 0 7 * 0 6 * 0 5 * 0 4 RESET TAO 0 $19 3 AC3 0 2 AC2 0 1 AC1 0 0 AC0 0
Bits 7-5 -- *Unused Unused bits read as zero. Reset TAO/TBO -- Reset Timer A and B Output TAO and TBO may be forced low at any time by writing a one to the reset location in TACR and TBCR. Output is held low during the write operation, and at the end of the bus cycle the output is allowed to toggle in response to a time-out pulse. When resetting TAO and TBO, the other bits in the TCR must be written with their previous value to avoid altering the operating mode. AC3-AC0/BC3-BC0 -- Select Timer A and B Operation Mode When the timer is stopped, counting is inhibited. The contents of the timer's main counter are not affected, although any residual count in the prescaler is lost.
AC3 BC3 0 0 0 0 0 0 0 0 1
AC2 BC2 0 0 0 0 1 1 1 1 0
AC1 BC1 0 0 1 1 0 0 1 1 0
AC0 BC0 0 1 0 1 0 1 0 1 0 Timer Stopped
OPERATION MODE
Delay Mode, / 4 Prescaler Delay Mode, / 10 Prescaler Delay Mode, / 16 Prescaler Delay Mode, / 50 Prescaler Delay Mode, / 64 Prescaler Delay Mode, / 100 Prescaler Delay Mode, / 200 Prescaler Event Count Mode
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AC3 BC3 1 1 1 1 1 1 1
AC2 BC2 0 0 0 1 1 1 1
AC1 BC1 0 1 1 0 0 1 1
AC0 BC0 1 0 1 0 1 0 1
OPERATION MODE Pulse Width Mode, / 4 Prescaler Pulse Width Mode, / 10 Prescaler Pulse Width Mode, / 16 Prescaler Pulse Width Mode, / 50 Prescaler Pulse Width Mode, / 64 Prescaler Pulse Width Mode, / 100 Prescaler Pulse Width Mode, / 200 Prescaler
TCDCR REGISTER BIT FIELD RESET ADDR 7 * 0 6 CC2 0 5 CC1 0 4 CC0 0 $1D 3 * 0 2 DC2 0 1 DC1 0 0 DC0 0
Bit 7, Bit 3 -- *Unused Unused bits read as zero. CC2-CC0/DC2-DC0 -- Select Timer C and D Operation Mode When the timer is stopped, counting is inhibited. The contents of the timer's main counter are not affected, although any residual count in the prescaler is lost.
CC2 DC2 0 0 0 0 1 1 1 1
CC1 DC1 0 0 1 1 0 0 1 1
CC0 DC0 0 1 0 1 0 1 0 1 Timer Stopped
OPERATION MODE
Delay Mode, / 4 Prescaler Delay Mode, / 10 Prescaler Delay Mode, / 16 Prescaler Delay Mode, / 50 Prescaler Delay Mode, / 64 Prescaler Delay Mode, / 100 Prescaler Delay Mode, / 200 Prescaler
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SECTION 7 UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS RECEIVER-TRANSMITTER
The universal synchronous asynchronous receiver-transmitter (USART) is a single, fullduplex serial channel with a double-buffered receiver and transmitter. There are separate receive and transmit clocks and, also, separate receive and transmit status and data bytes. The receive and transmit sections are also assigned separate interrupt channels. Each section has two interrupt channels: * one for normal conditions * another for error conditions All interrupt channels are edge-triggered. Generally, it is the output of a flag bit or bits which is coupled to the interrupt channel. Thus, if an interrupt-producing event occurs while the associated interrupt channel is disabled, no interrupt would be produced, even if the channel was subsequently enabled because a transition did not occur while the channel was enabled. That particular event would have to occur again, generating another edge, before an interrupt would be generated. The interrupt channels may be disabled and instead, a DMA device can be used to transfer the data via the control signals receiver ready (RR) and transmitter ready (TR). Refer to Section 7.4 DMA Operation for more information.
7.1 CHARACTER PROTOCOLS
The MFP USART supports asynchronous and, with the help of a polynomial generator checker, byte synchronous character formats. These formats are selected independently of the divide-by-one and divide-by-16 clock modes. It is possible to clock data synchronously into the MFP but still use start and stop bits. After a start bit is detected, data will be shifted in and a stop bit will be checked to determine proper framing. In this mode, all normal asynchronous format features apply. When the divide-by-one clock mode is selected, synchronization must be accomplished externally. The receiver will sample serial data on the rising edge of the receiver clock. In the divide-by-16 clock mode, the data is sampled at mid-bit time to increase transient noise rejection. Also, when the divide-by-16 clock mode is selected, the USART re-synchronization logic is enabled. This logic increases the channels clock skew tolerance. Refer to Section 7.1.1 Asynchronous Format for more information on the re-synchronization logic.
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7.1.1 Asynchronous Format
Variable character length and start/stop bit configurations are available under software control for asynchronous operation. The user can choose a character length from five to eight bits and a stop bit length of one, one and one-half, or two bits. The user can also select odd, even, or no parity. In the asynchronous format, start bit detection is always enabled. New data is not shifted into the receive shift register until a zero bit is received. When the divide-by-16 clock mode is selected, the false start bit logic is also active. Any transition must be stable for three positive receive clock edges to be considered valid. For a start bit to be good, a valid zeroto-one transition must not occur for eight positive receiver clock transitions after the initial one-to-zero transition. After a valid start bit has been detected, the data is checked continuously for valid transitions. When a valid transition is detected, an internal counter is forced to state zero, and no further transition checking is initiated until state four. At state eight, the "previous state" of the transition checking logic is clocked into the receiver. As a result of this re-synchronization logic, it is possible to run with asynchronous clocks without start and stop bits if there are sufficient valid transitions in the data streams.
7.1.2 Synchronous Format
When the synchronous character format is selected, the 8-bit synchronous character loaded into the synchronous character register (SCR) is compared to received serial data until a match is found. Once synchronization is established, incoming data is clocked into the receiver. The synchronous word will be continuously transmitted during an underrun condition. All synchronous characters can be optionally stripped from the receive buffer (i.e., taken out of the data stream and thrown away) by clearing the appropriate bit in the receive status register (RSR).
SCR REGISTER BIT FIELD RESET ADDR 7 D7 0 6 D6 0 5 D5 0 4 D4 0 $27 3 D3 0 2 D2 0 1 D1 0 0 D0 0
D7-D0 -- Data 0 = Cleared. 1 = Set. The synchronous character should be written after the character length is selected, since unused bits in the synchronous character register are zeroed out. When parity is enabled, synchronous word length is the character length plus one. The MFP will compute and append the parity bit for the synchronous character.
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7.1.3 USART Control Register (UCR)
This register selects the clock mode and the character format for the receive and transmit sections.
UCR REGISTER BIT FIELD RESET ADDR 7 CLK 0 6 CL1 0 5 CL0 0 4 ST1 0 $29 3 ST0 0 2 PE 0 1 E/O 0 0 0 U
CLK -- Clock Mode 1 = Data clocked into and out of receiver and transmitter at one sixteenth the frequency of their respective clocks. 0 = Data clocked into and out of receiver and transmitter at the frequency of their respective clocks. CL1-CL0 -- Character Length These bits specify the length of the character exclusive of start bits and parity.
CL1 0 0 1 1
CL0 0 1 0 1
CHARACTER LENGTH 8 Bits 7 Bits 6 Bits 5 Bits
ST1-ST0 -- Start/Stop Bit and Format Control These bits select the number of start and stop bits and specify the character format.
ST1 0 0 1 1
ST0 0 1 0 1
START BITS 0 1 1 1
STOP BITS 0 1 1-1/2 2
FORMAT Synchronous Asynchronous Asynchronous (See note) Asynchronous
NOTE: Used with divide-by-16 mode only.
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PE -- Parity Enable 1 = Parity checked by receiver and parity calculated and inserted during data transmission. 0 = No parity check and no parity bit computed for transmission. E/O -- Even/Odd Parity 1 = Even parity is selected. 0 = Odd parity is selected. Bit 0 -- Reserved by Motorola This bit is reserved and returns a zero when read.
7.1.4 USART Data Register (UDR)
This register is used to either provide the current data word in the receiver buffer or to provide data to the transmitter buffer.
UDR REGISTER BIT FIELD RESET ADDR 7 D7 0 6 D6 0 5 D5 0 4 D4 0 $2F 3 D3 0 2 D2 0 1 D1 0 0 D0 0
D7-D0 -- Data 0 = Cleared. 1 = Set.
7.2 RECEIVER
As data is received on the serial input line (SI), it is clocked into an internal 8-bit shift register until the specified number of data bits have been assembled. The character will then be transferred to the receive buffer, assuming that the last word in the receive buffer has been read. This transfer will set the buffer full bit in the receiver status register (RSR) and produce a buffer full interrupt to the processor, assuming this interrupt has been enabled. Reading the receive buffer satisfies the buffer full condition and allows a new data word to be transferred to the receive buffer when it is assembled. The receive buffer is accessed by reading the USART data register (UDR). The UDR is simply an 8-bit data register used when transferring data between the MFP and the CPU. Each time a word is transferred to the receive buffer, its status information is latched into the receiver status register (RSR). The RSR is not updated again until the data word in the receive buffer has been read. When a buffer full condition exists, the RSR should always be read before the receive buffer (UDR) to maintain the correct correspondence between data and flags. Otherwise, it is possible that after reading the UDR and prior to reading the RSR, a new word could be received and transferred to the receive buffer. Its associated flags would be latched into the RSR, writing over the flags for the previous data word. Thus, when
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the RSR was read to access the status information for the first data word, the flags for the new word would be retrieved.
7.2.1 Receiver Interrupt Channels
The USART receiver section is assigned two interrupt channels. One indicates the buffer full condition while the other channel indicates an error condition. Error conditions include overrun, parity error, frame error, synchronous found, and break. These interrupting conditions correspond to the OE, PE, FE, and F/S or B bits of the receiver status register. These flags will function as described in Section 7.2.2 Receiver Status Register whether the receiver interrupt channels are enabled or disabled. While only one interrupt is generated per character received, two dedicated interrupt channels allow separate vector numbers to be assigned for normal and abnormal receiver conditions. When a received word has an error associated with it and the error interrupt channel is enabled, an interrupt will be generated on the error channel only. However, if the error channel is disabled, an interrupt for an error condition will be generated on the buffer full interrupt channel along with interrupts produced by the buffer full condition. The receiver status register must always be read to determine which error condition produced the interrupt.
7.2.2 Receiver Status Register (RSR)
The RSR contains the receiver buffer full flag, the synchronous strip enable, the various status information associated with the data word in the receive buffer. The RSR is latched each time a data word is transferred to the receive buffer. RSR flags cannot change again until the new data word has been read. However, the M/CIP bit is allowed to change.
RSR REGISTER BIT FIELD RESET ADDR 7 BF 0 6 OE 0 5 PE 0 4 FE 0 $2B 3 FS OR B 0 2 M OR CIP 0 1 SS 0 0 RE 0
BF-- Buffer Full Receiver word is transferred to the receive buffer. Receiver buffer is read by accessing the USART data register. 1 = Receiver word transferred to buffer. 0 = Read by RSR. OE-- Overrun Error Overrun error occurs when a received word is to be transferred to the receive buffer, but the buffer is full. Neither the receiver buffer nor the RSR is overwritten. The OE bit is set after the receive buffer full condition is satisfied by reading the UDR. This error condition will generate an interrupt to the processor. The OE bit is cleared by reading the RSR. New data words will not be assembled until the RSR is read.
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1 = Receiver buffer full and incoming word received. 0 = Read by RSR. PE-- Parity Error 1 = Parity error detected on character transfer to receiver buffer. 0 = No parity error detected on character transfer to receiver buffer. FE -- Frame Error A frame error exists when a non-zero data character is not followed by a stop bit in the asynchronous character format. 1 = Frame error detected on character transfer to receiver buffer. 0 = No frame error detected on character transfer to receiver buffer. F/S or B -- Found/Search or Break Detect The F/S bit is used in the synchronous character format. When set to zero, the USART receiver is placed in the search mode. F/S is cleared when the incoming character does not match the synchronous character. 1 = Match found. Character length counter enabled. 0 = Incoming data compared to SCR. Character length counter disabled. The B bit is used in the asynchronous character format. this flag indicates a break condition which continues until a non-zero data bit is received. 1 = Character transferred to the receive buffer is a break condition. 0 = Non-zero data bit received and break condition was acknowledged by reading the RSR at least once. M or CIP -- Match/Character in Progress The M bit is used in the synchronous character format and indicates a synchronous character has been received. 1 = Character transferred to the receive buffer matches the synchronous character. 0 = Character transferred to the receive buffer does not match the synchronous character. The CIP bit is used in the asynchronous character format and indicates that a character is being assembled. 1 = Start bit is detected. 0 = Final stop bit has been received. SS -- Synchronous Strip Enable 1 = Characters that match the synchronous character will not be loaded into the receiver buffer and no buffer full condition will be produced. 0 = Characters that match the synchronous character will be transferred to the receive buffer and a buffer full condition will be produced.
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RE -- Receiver Enable This bit should not be set until the receiver clock is active. When the transmitter is disabled in auto-turnaround mode this bit is set. 1 = Receiver operation is enabled. 0 = Receiver is disabled.
7.2.3 Special Receive Conditions
Certain receive conditions relating to the overrun error flag and the break detect flag require further explanation. Consider the following examples: 1. A break is received while the receive buffer is full. This does not produce an overrun condition. Only the B flag will be set after the receiver buffer is read. 2. A new word is received, and the receive buffer is full. A break is received before the receive buffer is read. Both the B and OE flags will be set when the buffer full condition is satisfied.
7.3 TRANSMITTER
The transmit buffer is loaded by writing to the USART data register (UDR). The data character will be transferred to an internal 8-bit shift register when the last character in the shift register has been transmitted. This transfer will produce a buffer empty condition. If the transmitter completes the transmission of the character in the shift register before a new character is written to the transmit buffer, an underrun error will occur. In the asynchronous character format, the transmitter will send a mark until the transmit buffer is written. In the synchronous character format, the transmitter will continuously send the synchronous character until the transmit buffer is written. The transmit buffer can be loaded prior to enabling the transmitter. After the transmitter is enabled, there is a delay before the first bit is output. The serial output line (SO) should be programmed to be high, low, or high impedance (by setting the appropriate bits in the transmitter status register (TSR)) before the transmitter is enabled forcing the output line to the desired state until the first bit of the first character is shifted out. The state of the H and L bits in the TSR determine the state of the first transmitted bit after the transmitter is enabled. If the high impedance mode is selected prior to the transmitter being enabled, the first bit transmitted is indeterminate. Note that the SO line will always be driven high for one bit time prior to the character in the transmit shift register being transmitted when the transmitter is first enabled. When the transmitter is disabled, any character currently being transmitted will continue to completion. However, any character in the transmit buffer will not be transmitted and will remain in the buffer. Thus, no buffer empty condition will occur. If the buffer is empty when the transmitter is disabled, the buffer empty condition will remain, but no underrun condition will be generated when the character in transmission is completed. If no character is being transmitted when the transmitter is disabled, the transmitter will stop at the next rising edge of the internal shift clock.
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In the asynchronous character format, the transmitter can be programmed to send a break. The break will be transmitted once the word currently in the shift register has been sent. If the shift register is empty, the break command will be effective immediately. A transmit error interrupt will be generated at every normal character boundary to aid in timing the break transmission. The contents of the TSR are not affected, however. The break will continue until the break bit is cleared. The underrun error (UE) must be cleared from the TSR. Also, the interrupt pending register must be cleared of pending transmitter errors at the beginning of the break transmission, or no interrupts will be generated at the character boundary time. The break (B) bit cannot be set until the transmitter has been enabled and has had sufficient time (one transmitter clock cycle) to perform internal reset and initialization functions. Any character in the transmit buffer at the start of a break will be transmitted when the break is terminated, assuming the transmitter is still enabled. If the transmit buffer is empty at the start of a break, it may be written at any time during the break. If the buffer is still empty at the end of the break, an underrun condition will exist. Disabling the transmitter during a break condition causes the transmitter to cease transmission of the break character at the end of the current character. No end-of-break stop bit will be transmitted. Even if the transmit buffer is empty, no buffer empty condition will occur nor will an underrun condition occur. Also, any word in the transmit buffer will remain.
7.3.1 Transmitter Interrupt Channels
The USART transmit section is assigned two interrupt channels. The normal channel indicates a buffer empty condition, and the error channel indicates an underrun or end condition. These interrupting conditions correspond to the BE, UE, and END flags in the TSR. The flag bits will function as described in Section 7.3.2 Transmitter Status Register whether their associated interrupt channel is enabled or disabled.
7.3.2 Transmitter Status Register (TSR)
The TSR contains various transmitter error flags and transmitter control bits for selecting auto-turnaround and loopback mode.
TSR REGISTER BIT FIELD RESET ADDR 7 BE 0 6 UE 0 5 AT 0 4 END 0 $2D 3 B 0 2 H 0 1 L 0 0 TE 0
BE -- Buffer Empty 1 = Character in the transmit buffer transferred to TSR. 0 = Transmit buffer reloaded by writing to the USR. U -- Underrun Error One full transmitter clock cycle is required after UE bit is set before it can be cleared. This bit does not require clearing before writing to the UDR.
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1 = Character in the TSR was transmitted before a new word was loaded into the transmit buffer. 0 = Transmitter disabled or read performed on TSR. AT -- Auto-Turnaround When set, the receiver will be enabled automatically after the transmitter has been disabled and the last character being transmitted is complete. END -- End of Transmission If the transmitter is disabled while a character is being transmitted, this bit is set after transmission is complete. if no character was being transmitted, then this bit is set immediately. Re-enabling the transmitter clears this bit. B -- Break This bit only functions in the asynchronous format. When B is set, BE cannot be set. A break consists of all zeros with not stop bit. this bit cannot be set until transmitter is enabled and internal reset and initialization is complete. 1 = Break transmitted and transmission stops. 0 = Break ceases and normal transmission resumes. H, L -- High and Low These bits configure the transmitter output (SO) when the transmitter is disabled. Changing these bits after the transmitter is enabled will not alter the output state until END is cleared.
H 0 o 1 1
L 0 1 0 1
OUTPUT STATE High Impedance Low High Loopback Mode
TE -- Transmitter Enable The serial output will be driven according to H and L bits until transmission begins. A one bit is transmitted before character transmission in the TSR begins. 1 = Transmitter enabled. 0 = Transmitter disabled. The UE bit is cleared and the END bit is set.
7.4 DMA OPERATION
USART error conditions are valid only for each character boundary. When the USART performs block data transfers by using the DMA handshake lines receiver ready (RR) and transmitter ready (TR), errors must be saved and checked at the end of a block. This is accomplished by enabling the error channel for the receiver or transmitter and by masking
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interrupts for this channel. Once the transfer is complete, interrupt pending register A is read. Any pending receiver or transmitter error indicates an error in the data transfer. RR is asserted when the buffer full bit is set in the RSR unless a parity error or frame error is detected by the receiver. TR is asserted when the buffer empty bit is set in the TSR unless a break is currently being transmitted.
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SECTION 8 ELECTRICAL CHARACTERISTICS
This section contains the electrical specifications and associated timing information for the MC68HC901 multi-function peripheral. Refer to Section 9 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage, frequency, and temperature rating.
8.1 MAXIMUM RATINGS
RATING Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Power Dissipation NOTES: 1. SYMBOL VCC Vin TA Tstg PD VALUE - 0.3 to 7.0 - 0.3 to 7.0 0 to 70 - 65 to 150 0.21 UNIT V V C C W This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximumrated voltages to this highimpedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VCC or GND).
Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximumrated voltages.
2.
8.2 THERMAL CHARACTERISTICS
CHARACTERISTIC Thermal Resistance Plastic (Dual-In-Line) PLCC *Estimated SYMBOL JA VALUE SYMBOL JC VALUE RATING C / W 20* 30
40 60
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Electrical Characteristics
8.3 POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in C can be obtained from: TJ = TA + (PD * JA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (1) where: TA JA PD PINT PI/O = Ambient Temperature, C = Package Thermal Resistance, Junction-to-Ambient, C/W = PINT + PI/O = ICC x VCC, Watts -- Chip Internal Power = Power Dissipation on Input and Output Pins, Watts -- User Determined
For most applications PI/O < PINT and can be neglected. An appropriate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273 C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (2) Solving equations (1) and (2) for K gives: K = PD * (TA + 273 C) + JA * PD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the outside ambient (CA). These terms are related by the equation: JA = JC + CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (4) JC is device related and cannot be influenced by the user. However, CA is user dependent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal convection. Thus, good thermal management on the part of the user can significantly reduce CA so that JA approximately equals JC. Substitution of JC for JA in equation (1) will result in a lower semiconductor junction temperature.
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Electrical Characteristics
8.4 DC ELECTRICAL CHARACTERISTICS
(TA = 0 C to 70 C; VCC = 5.0 Vdc 5%; GND = 0 Vdc; unless otherwise noted)
CHARACTERISTIC SYMBOL VIH VIL VIH VIL VOH VOL ILL ILI ILOH ILOL IOH IOL MIN 2.0 - 0.3 3.15 - 0.3 2.4 -- -- -- -- -- -- -- MAX VCC 0.8 VCC 1.35 -- 0.5 40 10 10 - 10 - 400 5.3 UNIT V V V V V V mA A A A A mA
Input High Voltage, except XTAL1 Input Low Voltage, except XTAL1 XTAL1 Input High Voltage XTAL1 Input Low Voltage Output High Voltage, Except IRQ, DTACK (IOH = - 120 A) Output Low Voltage, Except DTACK (IOL = 2.0 mA) Power Supply Current Input Leakage Current (Vin = 0 to VCC) Hi-Z Output Leakage Current in Float (Vout = 2.4 to VCC) Hi-Z Output Leakage Current in Float (Vout = 0.5 V) DTACK Output Source Current (Vout = 2.4 V) DTACK Output Sink Current (Vout = 0.5 V)
8.5 CAPACITANCE
(TA = 25 C; f = 1 MHz; unmeasured pins returned to ground)
CHARACTERISTIC Input Capacitance Hi-Z Output Capacitance Load CapacitanceIRQ, DTACK All Other Outputs SYMBOL Cin Cout C MIN -- -- -- MAX 10 10 100 130 UNIT pF pF pF
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8-3
Electrical Characteristics
8.6 CLOCK TIMING
(See Figure 8-1)
NUM -- 1 2, 3 4, 5 CHARACTERISTIC Frequency of Operation Cycle Time Clock Pulse Width Rise and Fall Times SYMBOL f tcyc tCL, tCH tCr, tCf MIN 1.0 250 110 -- MAX 4.0 1000 485 15 UNIT MHz ns ns ns
1 2 2.0 V 0.8 V 3
4
5
Figure 8-1. Clock Input Timing Diagram
10 pF
Y1 5 pF
FIGURE - CLOCK INPUT TIMING DIAGRAM MC68HC901UM / AD XTAL1 Crystal Parameters: Parallel resonance fundamental mode AT cut < R S -- 150 (f = 2.8 - 4.0 MHz) MC68HC901 < R S -- 300 (f = 2.0 - 2.7 MHz) C L = 18 pF, C M = 0.02 pF, CR = 5 pF, L M = 96 MHz XTAL2 f (typical) = 2.4576 MHz
Figure 8-2. MFP External Oscillator Components
FIGURE - MFP EXTERNAL OSCILLATOR COMPONENTS MC68HC901UM / AD
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Electrical Characteristics
8.7 AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0 Vdc 5%; GND = 0 Vdc; TA = 0 C to 70 C; unless otherwise noted, see Figures 8-3 through 8-12)
CHARACTERISTIC CS, DS Width High R/W, RS1-RS5 Valid to Falling CS Setup Time Data Valid Prior to Falling CLK Setup Time (Write Cycle Only) CS, IACK Valid to Falling CLK Setup Time CLK Low to DTACK Low CS or DS or IACK High to DTACK High CS or DS or IACK High to DTACK High Impedance DTACK Low to Data Invalid Hold Time (Write) CS or DS or IACK High to Data High Impedance (Read) CS or DS High to RS1-RS5, R/W Invalid Hold Time Data Valid from CS Low (Read) Data Valid to DTACK Low Setup Time (Read) DTACK Low to DS or CS or IACK High Hold Time IEI Low to Falling CLK Setup Time IEO Valid from CLK Low Delay Time Data Valid from CLK Low Delay Time IEO Invalid from IACK High Delay Time DTACK Low from CLK High Delay Time IEO Valid from IEI Low Delay Time Data Valid from IEI Low Delay Time CLK Cycle Time CLK Width Low CLK Width High CS, IACK Inactive to Rising CLK Setup Time I/O Minimum Active Pulse Width IACK Width High I/O Data Valid from Falling CLK (Write) MIN 50 0 0 50 -- -- -- 0 -- 0 -- 50 0 50 -- -- -- -- -- -- 250 110 110 100 100 2 -- MAX -- -- -- -- 220 60 100 -- 50 -- 310 -- -- -- 180 300 150 180 100 220 1000 -- -- -- -- -- 450 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns
NUM 14 2 3 41 5 6 7 8 9 10 115 12 13 14 15 16 17 18 19 20 21 22 23 242,4 25 263 27
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Electrical Characteristics
NUM 28 29 30 313 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 493 50
CHARACTERISTIC Receiver Ready (RR) Delay from Rising RC Transmitter Ready (TR) Delay from Rising TC TxO (A or B) Low from Rising Edge of CS or DS (Reset Time) Timer Output (TxO) Valid from Falling tclk that Causes Timeout Timer Clock (tclk) Low Time Timer Clock (tclk) High Time Timer Clock (tclk) Cycle Time RESET Low Time Delay to Falling IRQ from Ix Active Transition Transmitter Interrupt Delay from Falling Edge of TC Receiver Interrupt Delay from Rising Edge of RC (Buffer Full) Receiver Interrupt Delay from Falling Edge of RC (Error) SI Setup Time from Rising Edge of RC (Divide by 1 Only) SI Hold Time from Rising Edge of RC (Divide by 1 Only) SO Data Valid from Falling Edge of TC (Divide by 1 Only) TC Low Time TC High Time TC Cycle Time RC Low Time RC High Time RC Cycle Time CS, IACK, DS Width Low SO Data Valid from Falling Edge of TC (Divide by 16 Only)
MIN -- -- -- -- 110 110 250 2 -- -- -- -- 80 350 -- 500 500 1.05 500 500 1.05 -- --
MAX 600 600 450 2 tclk + 300 -- -- 1000 -- 380 550 800 800 -- -- 440 -- -- -- -- 80 490
UNIT ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns s ns ns s tcyc ns
NOTES: 1. 2. 3.
If the setup time is not met, CS will not be recognized until the next falling clock. If this setup time is met (for consecutive cycles), the minimum hold-off time of one clock cycle will be obtained. If not met, the hold-off time will be two clock cycles. tcyc refers to the clock signal applied to the MFP CLK input pin. tclk refers to the timer clock signal, regardless of whether that signal comes from the XTAL1/XTAL2 crystal clock inputs or the TAI or TBI timer inputs. CS is latched internally, therefore if specifications 1 and 24 are met, then CS may be negated before the falling clock and still initiate a bus cycle. Although CS and DTACK are synchronized with the clock, the data out during a read cycle is asynchronous to the clock, relying only on CS for timing.
4. 5.
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Electrical Characteristics
8.8 TIMER AC CHARACTERISTICS
Definitions: Error = Indicated time value - actual time value tpsc = tCLK x Prescale Value Internal Timer Mode: Single Interval Error (Free Running) (See Note 2 below) . . . . . . . . . . . . . . . . 100 ns Cumulative Internal Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Error Between Two Timer Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (tpsc - 4 tCLK) Start Timer to Stop Timer Error . . . . . . . . 2 tCLK + 100 ns to - (tpsc + 6 tCLK + 100 ns) Start Timer to Read Timer Error . . . . . . . . . . . . . . . . . . . 0 to - (tpsc + 6 tCLK + 400 ns) Start Timer to Interrupt Request Error (See Note 3 below) . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 2 tCLK to - (4 tCLK + 800 ns) Pulse Width Measurement Mode: Measurement Accuracy (See Note 1 below) . . . . . . . . . . . . 2 tCLK to - (tpsc + 4 tCLK) Minimum Pulse Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 tCLK Event Counter Mode: Minimum Active Time of TAI and TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 tCLK Minimum Inactive Time of AI and TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 tCLK
NOTES: 1. 2. 3. Error may be cumulative if repetitively performed. Error with respect to tout or IRQ if note 3 is true. Assuming it is possible for the timer to make an interrupt request immediately.
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Electrical Characteristics
21 23 CLK 22 R/W 1 4 CS 24
DS 2 RS1 - RS5 11 D0 - D7 12 DTACK 6 13 7 5 9 10
Figure 8-3. Read Cycle Timing
CLK
FIGURE - READ CYCLE TIMING MC68HC901UM / AD 2 24
R/W 4 CS 1 DS 2 RS1 - RS5 10
D0 - D7 3 DTACK 6 13 7 5 8
Figure 8-4. Write Cycle Timing
FIGURE - WRITE CYCLE TIMING MC68HC901UM / AD
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Electrical Characteristics
CLK 4 IACK 26
DS 14 IEI 15 IEO 16 D0 - D7 6 DTACK 13 18 7 NOTE: IEO only goes low if no acknowledgeable interrupt is pending. If IEO goes low, DTACK and the data bus remain in the high-impendance state. (SEE NOTE) 9 17
Figure 8-5. Interrupt Acknowledge Cycle (IEI Low)
FIGURE - INTERRUPT ACKNOWLEDGE CYCLE (IEI Low) TIMING MC68HC901UM / AD
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Electrical Characteristics
CLK 4 IACK
DS
IEI 19 IEO 20 D0 - D7 18 DTACK 18 A (NOTE 2) 6 7 NOTES: 1. IEO only goes low if no acknowledgable interrupt is pending. If IEO goes low, DTACK and the data bus remain in the high-impedance state. 2. DTACK will go low at A if specification number 14 is met. Otherwise, DTACK will go low at B . B (NOTE 1) 9 17
Figure 8-6. Interrupt Acknowledge Cycle (IEI High)
FIGURE - INTERRUPT ACKNOWLEDGE CYCLE (IEI High) TIMING 25 MC68HC901UM / AD I7 - I0 36 IRQ
NOTE: Active edge is assumed to be the rising edge.
Figure 8-7. Interrupt Timing
FIGURE - INTERRUPT TIMING MC68HC901UM / AD 27
CLK
I7 - I0
Figure 8-8. Port Timing
FIGURE - PORT TIMING MC68HC901UM / AD
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Electrical Characteristics
35 RESET
Figure 8-9. Reset Timing
FIGURE - RESET TIMING 48 MC68HC901UM / AD 47 46 RC 28 RR 38 IRQ (BUFFER FULL CONDITION) 39 IRQ (ERROR CONDITION) SI (DIVIDE-BY-1 MODE ONLY) 40 41
Figure 8-10. Receiver Timing
FIGURE - RECEIVER TIMING 45 MC68HC901UM / AD 44 43 TC 29 TR 42 SO (DIVIDE-BY-16-MODE) 50 SO (DIVIDE-BY-1-MODE) 37 IRQ
Figure 8-11. Transmitter Timing
FIGURE - TRANSMITTER TIMING MC68HC901UM / AD
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Electrical Characteristics
34 33 32 XTAL1 / XTAL2 49 CS / DS / IACK
INTERNAL TIMEOUT 31 TAO / TBO / TCO / TDO
(SEE NOTE) 30
NOTE: Specification # 30 applies to timer outputs TAO and TBO only.
Figure 8-12. Timer Timing
FIGURE - TIMER TIMING MC68HC901UM / AD
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SECTION 9 MECHANICAL DATA AND ORDERING INFORMATION
This section contains the pin assignments, package dimensions, and ordering information for the MC68HC901 multi-function peripheral.
9.1 PIN ASSIGNMENTS
PACKAGE 48-Pin Dual-In-Line (Plastic) 52-Lead QUAD MC68HC901 Yes Yes
R/W RS1 RS2 RS3 RS4 RS5 TC SO SI RC VCC NC TAO TBO TCO TDO XTAL1 XTAL2 TAI TBI RESET I0 I1 I2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CS DS DTACK IACK D7 D6 D5 D4 D3 D2 D1 D0 GND CLK IEI IEO IRQ RR TR I7 I6 I5 I4 I3
Figure 9-1. 48-Pin Dual-In-Line Package (Plastic)
FIGURE - 48-PIN DUAL-IN-LINE PACKAGE
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MC68HC901 USER'S MANUAL MC68HC901UM / AD
9-1
Mechanical Data and Ordering Information
TC SO SI RC VCC NC NC TAO TBO TCO TDO XTAL1 XTAL2
8
RS5 RS4 RS3 RS2 RS1 R/W NC CS DS DTACK IACK D7 D6 7 1 52 47 46 D5 D4 D3 D2 D1 D0 GND CLK IEI IEO IRQ RR TR 20 21 34 33
Figure 9-2. 52-Lead QUAD Package
9.2 PACKAGE DIMENSIONS
FIGURE - 52-LEAD QUAD PLCC MC68HC901UM / AD
CASE PACKAGE 48-Pin Dual-In-Line (Plastic) 52-Lead QUAD
-A48 25 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). INCHES MIN MAX 2.415 2.445 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.070 BSC 0.008 0.015 0.115 0.150 0.600 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 61.34 62.10 13.72 14.22 3.94 5.08 0.36 0.55 1.02 1.52 2.54 BSC 1.79 BSC 0.20 0.38 2.92 3.81 15.24 BSC 0 15 0.51 1.01
1
NC TAI TBI RESET I0 I1 I2 I3 I4 I5 I6 I7 NC
MC68HC901 Yes Yes
-B24
TIP TAPER
DETAIL X
C
L
-TSEATING PLANE
K DETAIL X F D 32 PL 0.51 (0.020)
M
N J 48 PL 0.25 (0.010)
M
M 48 PL
G TA
S
T
B
S
DIM A B C D F G H J K L M N
Figure 9-3. Case 767-02-P Suffix
CASE 767-02 ISSUE B 9-2 MC68HC901 USER'S MANUAL DATE 01/31/90 MOTOROLA
Mechanical Data and Ordering Information
-N-
Y BRK
B
0.18 (0.007) U
M
TN
S
-P
S
L
S
-M
S
S S
0.18 (0.007) M T N
-P
LS -MS
NOTE 1 -L-M-
W
52 (NOTE 1) -P-
1 X V VIEW D-D A Z R 0.18 (0.007) M T L
S
G1 0.25 (0.010) M T N
S
-P
S
LS -M
S
0.18 (0.007) M T L
S
-M
S
N
S
-P
S
-M
S
N
S
-P
S
C E 0.10 (0.004) - T - SEATING PLANE
H
0.18 (0.007) M T L 0.18 (0.007) M T N
S S
- M S N S -P S -P S L S - M S
K1 K F 0.18 (0.007) M T L S - M S N S - P S 0.18 (0.007) M T N S - P S L S - M S
52 (NOTE 1)
G
J DETAIL S
G1 0.25 (0.010) M T L
S
-M
S
N
S
-P
S
DETAIL S NOTES: 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE REPRESENTED BY A GENERAL (SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 52 LEADS. 2. DATUMS -L-, -M -, -N-, DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T- , SEATING PLANE. 4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.25 (0. 010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO .012 (.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH. TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 8. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN .037 (.940). THE DAMBAR INSTRUSION(S) SHALL NOT CAUSE THE H DIMEMSION TO BE SMALLER THAN .025 (.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
MILLIMETERS MIN MAX 19.94 20.19 19.94 20.19 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 0.64 19.05 19.20 19.05 19.20 1.21 1.07 1.21 1.07 1.42 1.07 0.50 2 10 18.04 18.54 1.02
INCHES MIN MAX 0.785 0.795 0.785 0.795 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.750 0.756 0.750 0.756 0.042 0.048 0.042 0.048 0.042 0.056 0.020 2 10 0.710 0.730 0.040
Figure 9-4. Case 778-02-FN Suffix
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9-3
Mechanical Data and Ordering Information
9.3 ORDERING INFORMATION
PACKAGE TYPE MAXIMUM CLOCK FREQUENCY TEMPERATURE RANGE ORDER NUMBER
Plastic P Suffix Quad Pack FN Suffix 4.0 MHz 0 C to 70 C MC68HC901P
4.0 MHz
0 C to 70 C
MC68HC901FN
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INDEX
Numerics 48-Pin Dual-In-Line Package (Plastic) ..................................... 9-1 52-Lead QUAD Package ..................... 9-2 A AC Electrical Characteristics ............... 8-5 Active Edge Register (AER) ................ 5-1 AER register ........................................ 5-2 Asynchronous Bus Control .................. 2-2 Asynchronous Format .......................... 7-2 Automatic End-Of-Interrupt Mode ....................................... 4-12 B Bus Operation ...................................... 3-1 C Capacitance ......................................... Case Package Drawings Case 767-02-P Suffix .................... Case 778-02-FN Suffix .................. Character Formats Asynchronous ................................. Synchronous .................................. Character Protocols ............................. Clock Input Timing Diagram ................ Clock Signal ......................................... Clock Timing ........................................ Conceptual Circuit of Interrupt Source Selection ....................... Conceptual Circuits of an Interrupt Channel ..................................... D Daisy-Chained Interrupt Structure ....... 4-3 Daisy-Chaining MFPs .......................... 4-3 Data Bus Signals ................................. 2-2 8-3 9-2 9-3 7-2 7-2 7-1 8-4 2-2 8-4 6-2 4-9 Data Direction Register (DDR) ............. 5-2 Data Transfer Operations ..................... 3-1 DC Electrical Characteristics ................ 8-3 DDR register ........................................ 5-2 Delay Mode Operation ......................... 6-1 Diagram(s) Clock Input Timing .......................... 8-4 IACK Cycle Timing .......................... 3-3 Interrupt Acknowledge Cycle Timing (IEI High) ................ 8-10 Interrupt Acknowledge Cycle Timing (IEI Low) ................... 8-9 Interrupt Timing ............................. 8-10 MFP Block ...................................... 1-1 Port Timing ................................... 8-10 Read Cycle Timing .................. 3-2, 8-8 Receiver Timing ............................ 8-11 Reset Timing ................................. 8-11 Timer Timing ................................. 8-12 Transmitter Timing ........................ 8-11 Write Cycle Timing ................... 3-2, 8-8 Direct Memory Access Control Signals ....................................... 2-5 DMA Operation .................................... 7-9 E Electrical Characteristics ...................... 8-1 Event Count Mode Operation ............... 6-3 G General Purpose I/O Data Register (GPDR) ...................................... General Purpose I/O Interrupt Lines .......................................... General Purpose Input/Output Port ............................................ GPDR register ...................................... GPIP Control Registers ........................ GPIP Port ............................................. 5-1 2-3 5-1 5-1 5-1 5-1
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INDEX-1
Index
GPIP Registers Active Edge Register (AER) ........... 5-2 Data Direction Register (DDR) ....... 5-2 General Purpose I/O Data Register (GPDR) ................. 5-1 I IACK Cycle Timing Diagram ................ 3-3 IERA register ....................................... 4-4 IERB register ....................................... 4-5 IMRA register ....................................... 4-8 IMRB register ....................................... 4-9 Input and Output Signals ..................... 2-1 Interrupt Acknowledge Cycle (IEI High) ................................. 8-10 Interrupt Acknowledge Cycle (IEI Low) ................................... 8-9 Interrupt Acknowledge Operation ........ 3-2 Interrupt Channel Prioritization ............ 4-1 Interrupt Control Registers .................. 4-4 Interrupt Control Signals ...................... 2-3 Interrupt Enable Registers (IERA, IERB) ............................. 4-4 Interrupt In-Service Registers (ISRA, ISRB) ........................... 4-10 Interrupt Mask Registers (IMRA, IMRB) ........................... 4-8 Interrupt Pending Registers (IPRA, IPRB) ............................. 4-6 Interrupt Processing ............................ 4-1 Interrupt Registers Interrupt Enable Register A (IERA) .................................. 4-4 Interrupt Enable Register B (IERB) ................................. 4-5 Interrupt Mask Register A (IMRA) ................................. 4-8 Interrupt Mask Register B (IMRB) ................................ 4-9 Interrupt Pending Register A (IPRA) ................................. 4-6 Interrupt Pending Register B (IPRB) .................................. 4-7 Interrupt Service Register A (ISRA) ................................ 4-10 Interrupt Service Register B (ISRB) ................................ 4-11
INDEX-2
Vector Register (VR) ...................... 4-2 Interrupt Structure ................................ 4-1 Interrupt Timing .................................. 8-10 Interrupt Vector Number ...................... 4-1 Introduction .......................................... 1-1 IPRA register ........................................ 4-6 IPRB register ........................................ 4-7 ISRA register ...................................... 4-10 ISRB register ...................................... 4-11 K Key Features ........................................ 1-2 M Maximum Ratings ................................ MC68000 Family .................................. MC68HC901 Multi-Function Peripheral (MFP) ....................... Mechanical Data and Ordering Information ................................ MFP Block Diagram ............................. MFP External Oscillator Components .............................. MFP Register Map ............................... O Operation Modes ................................. 6-1 Ordering Information ............................ 9-4 P Package Dimensions ........................... 9-2 Pin Assignments .................................. 9-1 Port Timing ......................................... 8-10 Power Considerations .......................... 8-2 Power Supply Signals .......................... 2-1 programming registers .......................................... 1-2 Pulse Width Measurement Operation .................................. 6-2 R Read Cycle Timing ............................... Read Cycle Timing Diagram ................ Receiver ............................................... Receiver Interrupt Channels ................ 8-8 3-2 7-4 7-5 8-1 1-1 1-1 9-1 1-1 8-4 1-2
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MOTOROLA
Index
Receiver Timing ................................. 8-11 register programming ........................... 1-2 Register Select Bus Signals ................ 2-2 Reset Operation ................................... 3-3 Reset Signal ........................................ 2-2 Reset Timing ...................................... 8-11 RSR register ........................................ 7-5 S SCR register ........................................ 7-2 Section(s) Bus Operation ................................ 3-1 Electrical Characteristics ................ 8-1 General Purpose Input/Output Port ...................................... 5-1 Interrupt Structure .......................... 4-1 Introduction ..................................... 1-1 Mechanical Data and Ordering Information ........................... 9-1 Signal Description .......................... 2-1 Timers ............................................ 6-1 Universal Synchronous/ Asynchronous ReceiverTransmitter .......................... 7-1 Selecting the End-Of-Interrupt Mode ....................................... 4-11 Serial I/O Control Signals .................... 2-4 Signal Description ................................ 2-1 Signal Groups Asynchronous Bus Control ............. 2-2 Clock (CLK) .................................... 2-2 Data Bus (D7-D0) .......................... 2-2 DMA Control ................................... 2-5 GPIP Interrupts (I7-I0) ................... 2-3 Interrupt Control ............................. 2-3 Power Supply (VCC and GND) ....... 2-1 Register Select Bus (RS1-RS5) .......................... 2-2 Reset (RESET) ............................... 2-2 Serial I/O Control ............................ 2-4 Timer Control .................................. 2-4 Signal Summary .................................. 2-5 Software End-Of-Interrupt Mode ........ 4-12 Special Receive Conditions ................. 7-7 Synchronous Format ........................... 7-2
T Thermal Characteristics ....................... 8-1 Timer AC Characteristics ..................... 8-7 Timer Control Registers (TxCR) ........... 6-4 Timer Control Signals ........................... 2-4 Timer Data Registers (TxDR) ............... 6-4 Timer Registers Timer A Control Register (TACR) ................................. 6-4 Timer A Data Register (TADR) ................................. 6-4 Timer B Control Register (TBCR) ................................. 6-4 Timer B Data Register (TBDR) ................................. 6-4 Timer C and D Control Register (TCDCR) .............................. 6-4 Timer C Data Register (TCDR) ................................. 6-4 Timer D Data Register (TDDR) ................................. 6-4 Timer Timing ...................................... 8-12 Timers .................................................. 6-1 Transmitter ........................................... 7-7 Transmitter Interrupt Channels ............ 7-8 Transmitter Timing ............................. 8-11 TSR register ......................................... 7-8 U UCR register ........................................ UDR register ........................................ Universal Synchronous/Asynchronous Receiver-Transmitter ................. USART Registers Receiver Status Register (RSR) ................................... Synchronous Character Register (SCR) ................................... Transmitter Status Register (TSR) ................................... USART Control Register (UCR) ................................... USART Data Register (UDR) ......... V Vector Register (VR) ............................ 4-2 7-3 7-4 7-1
7-5 7-2 7-8 7-3 7-4
MOTOROLA
MC68HC901 USER'S MANUAL
INDEX-3
Index
VR register ........................................... 4-2 W Write Cycle Timing .............................. 8-8 Write Cycle Timing Diagram ................ 3-2
INDEX-4
MC68HC901 USER'S MANUAL
MOTOROLA

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